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Stanford Seminar -Drinking from the Firehose: How the Mill CPU Decodes 30+ Instructions per Cycle

stanfordonline · Youtube · 14 HN points · 1 HN comments
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"Drinking from the Firehose: How the Mill CPU Decodes 30+ Instructions per Cycle" -Ivan Godard, Out-of-the-Box Computing
Colloquium on Computer Systems Seminar Series (EE380) presents the current research in design, implementation, analysis, and use of computer systems. Topics range from integrated circuits to operating systems and programming languages. It is free and open to the public, with new lectures each week.

Learn more: http://bit.ly/WinYX5
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In one of the Mill talks, I've long since forgotten which, someone asks Ivan Godard a question about RISC. His response is something like "there was a brief window in the eighties where if you had a RISC machine you could get the whole computer onto one chip." I don't enough experience to know if this is right, but it strikes me as a nice clean explanation. It also explains why x86 won since then, because a couple generations later it was possible to get the whole computer onto one chip with x86 as well.

(I may have misquoted badly, in particular I'm not sure about the dates)

(edit: I found the talk, it's the last couple minutes of this: https://www.youtube.com/watch?v=LgLNyMAi-0I)

userbinator
there was a brief window in the eighties

This was also the very brief time when memory was actually faster than the core, making it possible to contemplate things like large fixed-with instruction encodings, since the main bottleneck with the early CISCs was instruction decoding and not fetch bandwidth; it is unlikely that, had this period not existed, RISC would have developed in the way that it had.

CalChris
It's ironic that Ditzel went from Berkeley RISC to Bell Labs and helped develop CRISP [1]. This was the invention of the Decoded Instruction Cache which solved the fetch/decode bandwidth problem. You could have a CISC and not have to worry about decode bandwidth. You could have a wide μop and not have to worry about fetch bandwidth.

[1] http://mprc.pku.edu.cn/~liuxianhua/chn/corpus/Notes/articles...

pkaye
My own understanding is more simple... people care mostly about application availability and x86 was chosen as the primary platform for Microsoft Windows so anything that didn't support the x86 instruction set was at a disadvantage. These days with interpreted or JIT compilation, things are less certain but those days running things on bare metal mattered.
CalChris
Your dates sound about right. The eighties. Mead+Conway was just out and fabs of a certain size became accessible. The question then was what could you do with these fabs and transistor budgets? Berkeley+Stanford did RISC+MIPS. Clark did the Geometry Engine at Stanford+SGI.

So what could you do with X transistors? But then X became stupid large. The 68000 (1979) had 40,000 transistors. Now the Apple A10 has 3.3-billion transistors. So you can imagine that architectural design assumptions dating from 1980 will need to be revisited.

rwallace
> The 68000 (1979) had 40,000 transistors.

Where did you get that figure? I'm curious because the figure I've seen tossed around is 68,000 transistors (the story going that this is where the model number came from).

CalChris
It's much more likely (like infinitely more likely) that the 68000 name stems from the earlier 6800 8-bit product line. There's nothing definitive saying 68,000 transistors and I've read both 40,000 and 68,000. I believe that 68,000 was just marketing. FWIW, Motorola also employed 68,000 people in 1980 (approximately):

https://www.motorolasolutions.com/content/dam/msi/docs/en-xw...

The Geometry Engine had 40,000.

https://books.google.com/books?id=gD4EAAAAMBAJ&pg=PA17&dq=68...

Dec 11, 2016 · 11 points, 1 comments · submitted by setra
RubyPinch
Does anyone have more interesting information about the existence of the hardware?
Aug 01, 2013 · 2 points, 0 comments · submitted by bowyakka
Jun 09, 2013 · 1 points, 0 comments · submitted by 6ren
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